1. Field of the Invention
The present invention relates generally to flash memory devices and, more specifically, to multi-level flash memory devices.
2. Description of Related Art
Flash memories (e.g., flash EEPROMs) are useful as subsidiary storage elements because they are capable of providing a large memory capacity with a higher degree of integration than traditional EEPROMs. NAND-type flash memories, in particular, typically have a higher integration density than other types of flash memories such as NOR- or AND-types. A memory cell of a flash memory is typically constructed by forming source and drain regions in a semiconductor substrate, forming a thin oxide film on the surface of the substrate between the source and drain regions, and then forming a floating gate, an interlayer oxide film, and a control gate on the substrate, in that order.
The NAND-type flash memory has several operation modes, including programming, erasing, and reading. The erasing and programming modes operate using a voltage difference between the floating gate and the substrate (or bulk). An erased memory cell is one in which electrons have moved into the floating gate from the substrate. When a read voltage is applied to an erased memory cell, current flows through the cell and it is detected as a logical “1”. A programmed memory cell, on the other hand, is one in which electrons have moved into the substrate from the floating gate. Programmed cells therefore have a higher threshold voltage than the erased cells and are detected as a logical “0”.
A multi-level flash memory provides additional data storage capacity using the same number of memory cells. Referring to FIG. 1, in a flash memory storing two bits per memory cell, there are four different possible distribution profiles of threshold voltages corresponding to logic states of “11”, “10”, “01”, and “00”. The “11” logic state, for example, corresponds to an erased state. Referring to FIG. 2, a multi-level flash memory can use a pair of latch circuits to load and sense the two data bits.
Referring to FIGS. 1 and 3A, in programming the two bits of the memory cell into one of the four data states, the wordline voltage W/Lm (m=1, 2, 3, . . . 15) sequentially steps up from VPGM1 (“10”) to VPGM2 (“01”) to VPGM3 (“00”), through repeated program cycles. In each program cycle, a program-verifying operation is carried out after completing the programming (or writing). As shown in FIG. 1, each program-verifying voltage VFYn−1 (where n=the number of data states (i.e., 4)) is set to the lowest position in each threshold distribution profile, while each reading voltage VRDn−1 is arranged at an intermediate position between the threshold distribution profiles.
FIG. 2 shows a number of memory strings in parallel, respectively connected to bit lines, BL1, BL2, BL3, and BL4, and also connected to a common source line CSL. Each memory string is controlled by a string select line SSL and a ground select line GSL. The two latch circuits in FIG. 2, LM and LL, are respectively assigned to the most significant bit (MSB) (e.g., “1” of “10”) and the least significant bit (LSB) (e.g., “0” of “10”). Outputs QM, QL of the latch circuits change in order of LSB-MSB-LSB during the programming and reading modes. The programming mode is operable with second and third latch control signals LTH2, LTH3, as in FIG. 3A, which are alternately active with high-leveled pulses, while a first latch control signal LTH1 is held at a low level. Latch selection signals SEL1, SEL2 also alternate in correspondence with their bits during every program/verifying cycle. The LSB latch node QL provides an output of the LSB latch circuit LL and always responds to a state of the MSB latch circuit LM when the LSB varies.
Referring now to FIG. 3A, during the programming mode, a program-inhibit state is entered while both latch outputs QM, QL are “1” (i.e., a “11” data state) to charge non-selected bitlines up to a power supply voltage (VCC) level. First, when programming the data state “10”, which is associated with the lowest threshold voltage, data bits “1” and “0” are loaded into the MSB and LSB latch nodes QM, QL, denoted in FIG. 3A as QM1 and QL0, respectively. The program voltage VPGM1 is then applied to a selected wordline (e.g., a control gate WL15 of a selected memory cell M), so that the selected memory cell M is forced to have its threshold voltage within the profile ΔVP1 of FIG. 1. The bitline BL1, shown in FIG. 2, is then set to a VSS level.
Following these steps, a program-verifying voltage VFY1 is applied to the selected wordline WL15 to evaluate whether the memory cell M has a threshold voltage within the profile of the data state “10”. If the threshold voltage of the memory cell M is within ΔVP1, the memory cell M is turned on in response to the program-verifying voltage VFY1 and the LSB latch output QL is thereby changed to “1” from “0”. The transition of the LSB latch output QL to “1” requires that the MSB latch output QM of “1” is coupled to the gate of the fourteenth NMOS transistor N14 and that a high level second latch control signal LTH2 is coupled to the gate of the fifteenth NMOS transistor N15.
Next, in programming the selected memory cell M into the data state “01”, a second program voltage VPGM2, which is higher than the first program voltage VPGM1, is applied to the memory cell M after programming it to the data state “10”. Data bits “0” and “1” are each loaded into the MSB and LSB outputs QM, QL, denoted in FIG. 3A as QM0 and QL1, respectively, and the first latch selection signal SEL1 is activated to supply a VSS voltage level to the first bitline BL1. After completing the second programming, if the threshold voltage of the selected memory cell M moves into the distribution profile ΔVP2 from ΔVP1, of FIG. 1, the second program-verifying voltage VFY2 changes the MSB latch output QM to “1” when the third latch control signal LTH3 is enable with a high-level pulse.
Finally, when programming the selected memory cell M into the data state “00”, the third program voltage VPGM3, which is higher than the second program voltage VPGM2, is applied to the selected memory cell M after programming it to the data state “01” (e.g., from “10” to “01”). At this time, the MSB latch output QM retains a value of “0”, which was set when programming “01”, and a newly loaded data bit “0” is transferred to the first bitline BL1. After completing the third programming, if the threshold voltage of the selected memory cell M moves into the distribution profile ΔVP3 from ΔVP2, of FIG. 1, the third program-verifying voltage VFY3 changes the LSB output QL to “1” when the second latch control signal LTH2 is enabled with a high-level pulse. During program-verifying, the LSB latch node QL is changeable when the MSB latch node QM is “1” and the second latch control signal LTH2 is at a high level.
Referring to FIG. 3B, a read operation mode proceeds in order from “00” to “01” to “10”, denoted in the right column of FIG. 3B. While transitioning the LSB latch node QL relies on feedback from the MSB latch node QM during the program-verifying operation, the read mode uses feedback from the complement of the MSB latch node QMB to change a state of QL. In the reading mode, the first and third latch control signals LTH1 and LTH3 alternate in accordance with reading cycles (e.g., LTH1 to LTH3 to LTH1), while the second latch control signal LTH2 is held at a low level. The latch outputs QM, QL are initiated at low levels, shown in the left of FIG. 3B, because the latch selection and control signals are disabled at the initial state.
First, in reading the data state “00” (00 RD), the third read voltage VRD3 is applied to the selected wordline WL15 coupled to the selected memory cell M. Because the third read voltage VRD3 is positioned between the distribution profiles of “00” and “01”, a memory cell M that has been programmed as “00” becomes conductive. The second latch selection signal SEL2 is also active, and the MSB latch node QM is “0” and the LSB latch node QL is “1” in response to a high-level pulse on the first latch control signal LTH1. At this time, the complementary MSB latch node QMB, which is established as “1”, feeds back to the gate of the sixteenth NMOS transistor N16, and the complement of the LSB latch node QLB thereby becomes “0” (QL=“1”), the value of which is shown on the right side of FIG. 3B.
When reading the data state “01” (01 RD), the first latch selection signal SEL1 is active with a high level and the second latch selection signal SEL2 is at low level. The third read voltage VRD3 turns the selected memory cell M on (VRD3>ΔVP2), and the latch outputs QM, QL are both “0”. Because the second read voltage VRD2 is lower than the third read voltage VRD3 and is interposed between the “01” and “10” levels, it cannot turn the selected memory cell M on. The MSB latch node QM therefore goes to “1” in response to a high-level pulse on the third latch control signal LTH3.
Reading the data state “10” (10 RD) is operable with the second latch selection signal SEL2 at a high level and the first latch selection signal SEL1 at a low level. As noted above, the latch nodes QM, QL are both maintained at “0” when the selected memory cell M is turned on by the application of the third read voltage level VRD3. In addition, the LSB latch node QL is maintained at “0” during the application of the second read voltage level VRD2. However, during application of the first read voltage level VRD1, which is lower than the second read voltage level VRD2, the LSB latch node QL changes to “1”. The LSB latch node QL transitions in response to feedback from the complementary MSB latch node QMB, which is applied to the gate of the sixteenth NMOS transistor N16.
An upper margin ΔUn−1 (where n=the number of data states (i.e., 4)), shown in FIG. 1, is the voltage gap between a read voltage VRDn−1 and a corresponding program-verifying voltage VFYn−1. A lower margin ΔLn−1, also shown in FIG. 1, is the voltage gap between the highest voltage of each distribution profile and the next higher read voltage VRDnA. The program-verifying and reading operations may be more easily carried out when the upper and lower margins are larger. However, the margin limits must also be considered because margins that are too large increase the threshold voltages of the highest distribution profile and also increase read voltages, regardless of program states. A higher read voltage can cause a soft program, which degrades the reliability of data states. Meanwhile, the narrowing of wordline pitches to provide higher integration density, induces capacitance coupling between wordlines and causes a wider spread in the distribution profiles. Adjusting the distribution profiles of threshold voltages is therefore a very important design consideration in a flash memory.
Flash memories may be exposed to various environments because they are used in portable electronic devices such as cell phones, personal digital assistants (PDAs), and other devices. Threshold voltage profiles of the flash memories are sensitive, however, to temperature variation during programming and reading.
FIGS. 4A-4D are graphs illustrating the effect of temperature on programming and reading operations. FIG. 4A shows that there is no problem if the programming and reading operations are performed at the same temperature, regardless of whether it is a high or a low temperature. Specifically, referring to FIG. 4A, the upper and lower margins ΔUn−1, ΔLn−1, are constant when the programming and reading operations are carried out at the same temperature with fixed program-verifying and reading voltages, regardless of what that temperature is. However, referring to FIGS. 4B through 4D, when the programming and reading operations are carried out at temperatures different from each other, migration of the threshold profiles reduces the margins and causes reading failures.
Referring specifically to FIG. 4B, when the programming operation is performed at a high temperature and the reading operation is performed at a low temperature, the profiles are shifted higher by a threshold voltage amount ΔVtn after programming. A weak inversion condition causes cell current to flow through a memory cell in proportion to temperature when the control gate of the memory cell is charged up near the program voltage. A high temperature may induce hot electrons and increase the amount of current flowing into the latch/sensing circuits shown in FIG. 2 above a pure cell current amount. During the program-verifying operation, the latch/sensing circuits therefore respond to currents less than cell currents corresponding to the desired threshold profiles. This, in turn, causes a termination of the programming operation before a normal end thereof. As a result, read voltages used at a low temperature need to be higher to generate cell currents identical to those resulting from the programming mode performed at a high temperature.
FIG. 4C illustrates a read operation performed at a high temperature after a program operation performed at a low temperature. In this case, the threshold distribution profiles migrate to the lower side. The high temperature during the read operation induces hot electrons that cause more current to flow into the latch/sensing circuits.
Misalignments between the temperature-dependent threshold profiles and the fixed wordline voltages of program-verifying and reading operations cause malfunctions in the programming and reading operations. And, as shown in FIG. 4D, these misalignments cause the threshold distribution profiles to be spread out on both the lower and higher sides, resulting in instability of establishing and sensing multi-level data states. Because there are limits in the amount by which the reading (and program-verifying) voltage ranges can be extended, and limits in the regulation of the upper and lower margins, fluctuations of voltage profiles due to temperature variations degrade the reliability of multi-bit flash memories.